Recently, with the high performance of the multimedia equipment, etc., the high density in the mounting technology serving as the interface between LSI and the electronic equipment is proceeding.
As the IC package responding to such request, there is the CSP (Chip Size Package) which is packaged in substantially equal size to the chip size. Further, the wafer level CSP from which individual CSPs are obtained by applying the film formation, the processing, etc. associated with the CSP structure in a wafer level, and then dicing such wafer, is known.
In the wafer level CSP, the rewiring is formed to be connected to the connection pads of the silicon wafer in which the transistors are formed, and then the bump electrodes are formed on the rewiring.
In Patent Literature 1 (Japanese Patent No. 4121542) and Patent Literature 2 (Japanese Patent No. 4431628), it is set forth that an insulating layer is formed on a semiconductor substrate having bump electrodes such that upper parts of the bump electrodes are exposed, and then wiring patterns connected to the bump electrodes are formed.
In Patent Literature 3 (Japanese Laid-Open Patent Publication No. 2002-43753), it is set forth that an insulating resin layer and a copper foil are laminated on the inner layer wiring plate, then openings are formed in the copper foil, then non-penetration holes are formed in the insulating resin layer through the opening in the copper foil by the blasting process, and then conductor circuit patterns are formed in the non-penetration holes by the plating.
In the semiconductor device having the CSP structure in the prior art, in most cases the rewiring formed on the silicon wafer is formed as a single layer, and therefore employment of the multilayer wiring structure is not considered at all (for example, Patent Literatures 1 and 2). In particular, in the semiconductor devices such as ASI, Logic, etc., it is required that the rewiring having the multilayer structure should be formed in order to correspond to the multi-pin type.
Further, in the prior art, the reliability in mounting the semiconductor device onto the mounting substrate is not considered. Therefore, such a problem exists that the conduction failure is caused due to the fact that a stress is concentrated in the external connection terminals of the semiconductor device at a time of mounting.